Hardware IP Gets A Major Update
By Mat Dirjish
Boasting superior NN acceleration for production L2-L3 automotive artificial intelligence (AI), the latest release of AImotive’s aiWare3 hardware IP includes significantly better host CPU offload, lower memory bandwidth, and upgraded SDK tools to enable scalable, low-power, low latency designs operating at speeds up to 100+ TOPS. Each aiWare3P hardware IP core offers up to 16 TMAC/s (>32 TOPS) at 2 GHz, with multi-core and multi-chip implementations capable of delivering up to 50+ TMAC/s (>100 INT8 TOPS).
The core is designed for AEC-Q100 extended temperature operation and includes a range of features to enable users to achieve ASIL-B and above certification. Key upgrades include:
- Enhanced on-chip data reuse and movement, scheduling algorithms, and external memory bandwidth management.
- Improvements ensure that 100% of most NNs execute within the aiWare3P core without host CPU intervention.
- A range of upgrades that reduce external memory bandwidth requirements.
- Advanced cross-coupling between C-LAM convolution engines and F-LAM function engines.
- Physical tile-based microarchitecture, enabling easier physical implementation of large aiWare cores.
- Logical tile-based data management, enabling efficient work load scalability up to the maximum 16 TMAC/s per core.
- Significantly upgraded SDK, including improved compiler and new performance analysis tools.
The aiWare3P hardware IP is being deployed in L2/L2+ production solutions, as well as studies of advanced heterogeneous sensor applications. The aiWare3P RTL will be shipping from January 2020. For more details, pay a visit to AImotive. And don’t forget to sign up for Sensors Daily Updates. It’s free, fast, and outstandingly easy. For a media kit and highly-effective sponsorship opportunities, contact Michael Mitchell via email at firstname.lastname@example.org.