Optimized NAND Flash Meets User Requirements
By Mat Dirjish
In the quest for achieving a balance between cost and performance in may sensor applications, Apacer can optimize NAND Flash memory to provide users with the amount of P/E cycles that best suits their design. Simply put, users will be paying only for what they need.
The company previously developed one form of NAND Flash optimization known as SLC-lite, which makes 2D MLC behave like SLC. MLC contains two bits, but by programming only one of the two bits, the least significant bit (LSB), the cell distribution behaves almost identically to that of SLC flash. The endurance is then increased, reaching 20,000 P/E cycles. Standard 2D MLC can only reach 3,000 P/E cycles.
Looking at mature 3D NAND Flash technology, the company has developed a similar process to SLC-lite for 3D NAND drives, yielding two new forms called SLC-liteX and MLC-liteX. SLC-liteX is based on 3D NAND technology. The firmware is tweaked to offer the greatest number of P/E cycles in this format: 30,000 cycles. Allegedly, this is 10 times more than MLC or industrial 3D TLC. As a result, the longest lifespans are available at a reasonable price point.
MLC-liteX is also based on 3D NAND technology. The firmware is tuned to offer more than three times as many P/E cycles (10,000) than MLC or industrial 3D TLC. Cost-benefit optimization is achieved while lifespans are still extended.
The standard bit format for 3D NAND TLC stores three bits in one cell. MLC-liteX programs only two of the three bits, so the capacity of MLC-liteX is only reduced by a third. The advantage of this tradeoff is that P/E cycles are increased. Continuing in this vein, SLC-liteX programs only one of the three bits. The capacity is therefore reduced by two-thirds, but even more P/E cycles are available. For more details, visit Apacer Technology.